There are a variety of different types of high-performance analog-to-digital converter circuits, including those commonly known as delta-sigma converters, and those commonly known as pipelined converters. The present invention relates to high-performance pipelined analog-to-converters. In the design of these pipelined converters, the designer is normally limited in the linearity that can be obtained. This is due primarily to accuracy limitations in reconstruction digital-to-analog converters which are used within the pipeline. This is particularly true for the reconstruction digital-to-analog converter in the first stage of the pipeline, since the accuracy of that stage has the greatest influence on the overall accuracy of the system.
Currently, the most common way to implement pipelined converters is to use switched capacitor techniques. In particular, a reconstruction digital-to-analog converter is implemented by providing a bank of capacitors, and by switching each of the capacitors between two reference levels under control of a digital code which is applied to the reconstructing converter for purposes of generating a corresponding analog signal. In theory, the capacitors should all have the same ideal capacitance value, but in practice there are usually variations. The accuracy or linearity of the reconstructing converter is therefore limited by the extent to which the capacitors can be matched to each other, or in other words the extent to which the capacitors can be manufactured so that variations from an ideal capacitance value are minimized. To the extent that there is mismatch between the capacitors in a reconstructing converter in a stage of a pipeline converter, the result is undesirable error in the analog residue signal passed to a subsequent stage, which results in harmonic distortion in the digital output of the overall pipelined analog-to-digital converter. Although it is possible to address this problem to some extent through trim or background calibration of the capacitors, this is often not an efficient or desirable approach.
From the foregoing, it may be appreciated that a need has arisen for a method and apparatus of effecting pipelined analog-to-digital conversion in a manner which reduces or avoids nonlinearities such as harmonic distortion. According to the present invention, a method and apparatus are provided to address this need, and involve effecting pipelined analog-to-digital conversion in first and second stages of conversion which each use an analog input to facilitate generation of an analog output and a multi-bit digital output, the analog input of one of the first and second stages being derived from the analog output of the other of the first and second stages. The first stage of conversion involves effecting an analog-to-digital conversion of the analog input of the first stage so as to generate a multi-bit digital output that is based on the analog input of the first stage and that serves as the multi-bit digital output of the first stage. The first stage further involves shuffling a plurality of switching signals derived from the multi-bit digital output of the analog-to-digital conversion so as to generate a plurality of shuffler output signals, the shuffling being effected according to a mapping function which relates each shuffler output signal to a respective switching signal, and the shuffling including dynamic variation of the mapping function so as to dynamically vary which of the shuffler output signals corresponds to which of the switching signals. The first stage also involves generating an analog residue signal which represents a difference between a magnitude corresponding to the analog input of the first stage and a magnitude corresponding to the multi-bit digital output of the analog-to-digital conversion, including selective switching of each of a plurality of circuit portions to one of first and second states in response to a respective shuffler output signal, the first and second states being different, and the analog residue signal serving as the analog output of the first stage, and having a magnitude which is a function of the number of the circuit portions which are switched so as to be in the first state.